Fe₂🦀₃⋅H₂🦀 on Nostr: after scouring everything I finally came across word for word the issue I'm having. ...
after scouring everything I finally came across word for word the issue I'm having. So, if I understand this right, to be safe what I should do is make a dummy buffer with the combined resource properties and cache the alignment requirements, then use the largest alignment for all subresources.
Maybe I could have sub buffers aligned on specific resource boundaries but I'm not sure if that's actually safe or would provide any benefit.
What I'm currently trying to figure out is if I have vertex and index memory within the same buffer what are the alignment requirements on that. At first glance the spec does not seem to say anything about it but I know that's not possible. NVidia says over and over to do that strategy but they don't ever say how.
The closest thing I've found seems to state that the vertices need to be aligned to their first individual element boundary, but theres a range of answers from "pretend you're allocating a buffer and use that" to "it depends on the hardware lmfao"
Published at
2025-05-06 13:56:54Event JSON
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"content": "after scouring everything I finally came across word for word the issue I'm having. So, if I understand this right, to be safe what I should do is make a dummy buffer with the combined resource properties and cache the alignment requirements, then use the largest alignment for all subresources. \n\nMaybe I could have sub buffers aligned on specific resource boundaries but I'm not sure if that's actually safe or would provide any benefit.\n\nnostr:nevent1qy2hwumn8ghj7un9d3shjtnddaehgu3wwp6kyqpq060vjwzca6shwamhchlcar687hydsqeul25kztuaa5rkjjwcsfusz73j3z\n\nhttps://s3.clubcyberia.co/pleroma/9f69c72865bc1cb896626baa1372a2993ce16baded690fba074a8ac1e28db46f.png",
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