Dave Anderson on Nostr: Ooh and you mentioned the CPU is static and can be halted consequence-free at any ...

Ooh and you mentioned the CPU is static and can be halted consequence-free at any point. What's the builtin debug facilities look like? Because if the FPGA's in charge of the CPU clock, you could maybe have a debug interface on GARY that lets you jack into the machine, halt the CPU on some trigger condition, inspect system state (assuming the CPU can be made to hi-Z its bus outputs, so the FPGA can take over as bus master and query RAM and whatever)...

Another pony for the list!