RISC-V
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
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[@risc_v](https://noc.social/@risc_v ) twitter feed
[Will be handed over to twitter account owner upon request]
Owner: jeancf (npub13n4…ednu)
Powered By: https://gitlab.com/jeancf/twoot
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npub1pmxdfms8nam7apu4w444q8y4z2r6gmc30t2k85pmdhf8y54g297shewhvv