Framework making a RISC-V mainboard is neat, but
- RISC comes with a ton of downsides
- x86 machines use micro-ops on the backend anyway, so after decode there's not really any difference between RISC and CISC.
If you could cut down the legacy bullshit of x86, it'd be a better, more efficient architecture than ARM or RISC, and a ton of that has to do with code size.
Ryan /
npub1gf…h659t
2024-06-18 15:08:04
Author Public Key
npub1gfv24p8uhe6pmc07apy82msp2xspep6zt0rjaelrayca2685z73s7h659tPublished at
2024-06-18 15:08:04Event JSON
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