Dave Anderson on Nostr: Consecutive as in the FPGA would receive first 8 bits on one PHI2 edge, and the other ...

Consecutive as in the FPGA would receive first 8 bits on one PHI2 edge, and the other 8 bits on the immediately following PHI2 edge?

Offhand that feels doable. Reads are the harder bit there, if you're clocking at ~12MHz, and the FPGA is at 25MHz, and the bus has no clock stretching mechanism to let the FPGA delay its response.Writes are easier, can just latch the two writes into registers and process them at leisure.

Big Q for ice40 is how fast I can clock the logic...