NOTimothyLottes on Nostr: Something I've never really understood about AMD's compiler. The hardware has some ...

Something I've never really understood about AMD's compiler. The hardware has some amazing and 'free' buffer addressing logic (image below), and yet the compiler seems to just ignore it.

For example,
int a=...;
int d=ssbo.array[(0xDEAD0000>>2)+a];

Generates
v_lshlrev_b32 v0, 2, v0
v_add_nc_u32 v1,lit(0xdead0000),v0
buffer_load_dword v1, v1, s[0:3], 0 offen

There is NO need for those VALU ops, the HW buffer addressing can add 0xdead0000 from an SGPR and scale 'a' by 4 (via const_stride)