Dave Anderson on Nostr: If the core only acts upon the write data register once the write signal has crossed ...

If the core only acts upon the write data register once the write signal has crossed clock domains, that... might? Be fine? But I'm not left with a strong sense of "yup definitely fine", or a clear idea of where one clock domain ends and another begins, tbh. Given gateware whose entire job is mediating across CPU, internal and video clock domains, I was hoping for much more brightly drawn lines around each one