Dave Anderson on Nostr: Hmm, another possibility, in the vera verilog I see a worrying amount of stateful ...

Hmm, another possibility, in the vera verilog I see a worrying amount of stateful logic that seems to trigger on level rather than posedge/negedge... I wonder if the issue you hit is because vera as-is is grabbing the bus data when the write signal is at the enable _level_, rather than only on transition. That would keep it latching repeatedly all the way to the end of the bus cycle, which, with unsynced clocks, now I can see where a delay in dropping /WR would lead to sadness