Dave Anderson on Nostr: Depends a lot on the bus timing requirements from the CPU. Roughly, with an async ...

Depends a lot on the bus timing requirements from the CPU. Roughly, with an async bus, the fastest the FPGA can turn around a read request is 3 cycles of its main clock (2 for clock domain crossing, 1 for memory access assuming no contention). I think ideally 4 cycles would be better, that'd allow for another layer of registers on the output to shorten the data paths.

On the 65C816, looks like reads need to be turned around in 0.5 PHI2 cycles. So, 3-4 cycles per half-PHI2.