VERA does not have an output enable line, only a chip select, which must be asserted (low) for any activity to occur.
Write takes priority over read, so you should be able to safely tie /RD low, if you like.
https://github.com/swetland/vera-module/blob/rev4/fpga/source/top.v#L218
Brian Swetland /
npub1pc…5rjk8
2024-07-15 04:06:14
in reply to nevent1q…d4e2
Author Public Key
npub1pcxszqyeekhg5uy4qrjx4jk65sq223xukk3azt8h4lhg724e7n3qg5rjk8Published at
2024-07-15 04:06:14Event JSON
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