Dave Anderson on Nostr: Cool, so assuming enough pins to do the thing, the FPGA could, say, let you ...

Cool, so assuming enough pins to do the thing, the FPGA could, say, let you inspect/modify RAM on a running machine by pausing the CPU clock, yanking BE to get the CPU off-bus, and initiate I/O with other peripherals itself. That could be fun.

The 65C816S datasheet's architecture diagram does show a bus enable control line on the I/O, so... maybe?