mos_8502 :verified: on Nostr: From Joe Burks: > VERA needs at least 3 full clock cycles between reads/writes to ...

From Joe Burks:

> VERA needs at least 3 full clock cycles between reads/writes to ensure that later accesses don't clobber older ones. It would seem this would always work since 3x25MHz = 120ns < 1x8MHz=125ns. However this must be measured from when the 25MHz clock samples the bus. In very unlucky instances, VERA could sample the bus almost 1 clock after it arrives. Therefore, if 4 cycles or more are given between writes (4 x 25MHz = 160ns), everything should always work fine; at 8MHz they come in with 125ns spacing. I was able to implement a simple FIFO in the VERA design that seemed to always work with writes, even at 10MHz, however the same strategy did not work in all cases with reads. As I recall, this primarily affected the newer FX feature set that isn't in Frank's original repo.