Hmm, and PHI2 is clocked at 8MHz when it's talking to vera, correct?
Looking at the verilog, I see it synchronizing the read and write signals across the clock domains... But not the data bits itself, those get latched into a register based on CPU signals (i.e. driven by CPU clock), and I'm not seeing any further domain crossing gubbins there... But this code also seems to play quite fast and loose with synchronization, so I'm having some trouble following the bits around...
Dave Anderson /
npub1mt…xwant
2024-08-04 22:21:11
in reply to nevent1q…54er
Author Public Key
npub1mtg38agwglttl7melxnfqphlm95uymnrdedw62h9j7cyquynza0szxwantPublished at
2024-08-04 22:21:11Event JSON
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