Addendum:
When I say this hypothetical hardware is almost entirely memory...
The "Parsing Unit" is a lookuptable determining the next lookuptable to consult. A couple twists on that concept, but still... This is the bulk of compute!
The "Output Unit" is another lookuptable & a couple decoders.
I chose an NPU that's a twist on flash memory.
The Tree-SIMT "Layout Coprocessor" has a large shift memory per core, powering tree traversals.
Arithmetic Core has more RAM than ALU...
5/4 Fin!
Adrian Cochrane /
npub186…snt98
2024-06-27 20:31:37
in reply to nevent1q…3taq
Author Public Key
npub186lgefknfnkgychnfjancqnv4k4yrdzxal486lw0p80z6vmley9qgsnt98Published at
2024-06-27 20:31:37Event JSON
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