Is it possible to multiply a clock in a Verilog testbench? It absolutely does not need to be synthesizable, this is purely for simulation
I can generate clocks of different frequencies with "always begin" + delays but I want to guarantee a edge alignment or a phase shift
Boosts for visibility appreciated!
#verilog #fpga #hardware #openhardware
Amini Allight /
npub1me…pyhxc
2024-07-18 01:47:29
Author Public Key
npub1meg7lu0ezlj444zyhtcr2cwe0y78ndcr0qrkhj2trjzchmfc9edq8pyhxcPublished at
2024-07-18 01:47:29Event JSON
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