Did you ever found firmwares for Tricore or v850 architectures accessing addresses starting with 0xa.. instead of the 0x80.. one? after so much research I end up learning that this is handled by the mmu which applies a cache layer on top of the same memory range. In other words: IDA lies by fake the references by dropping the 3rd bit, ghidra can't handle this, and r2 is again the only tool able to properly define this memory layout.
https://community.infineon.com/t5/AURIX/About-the-issue-with-lsl-files/td-p/676113#.
pancake :verified: /
npub1en…6wye5
2024-08-31 14:30:10
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wss://relay.momostr.pinkPublished at
2024-08-31 14:30:10Event JSON
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