Dave Anderson on Nostr: if I'm reading this right, you can configure the CPU to stretch PHI2 for slower ...

if I'm reading this right, you can configure the CPU to stretch PHI2 for slower memories, which may end up being required here. Otherwise running at 12.5MHz PHI2, FPGA has to turn reads around at 25MHz, so 75-100MHz internal clock. That _should_ be doable, simple experimental designs clear 150MHz easily, but I don't know what the more complex vera-ish bus frontend will need.