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"content": "Oh for sure, in terms of input hardware I'm fairly sure I'll do north of 50MHz (haven't looked at the spec sheet though). My recollection is the problem is more clock domain crossing when there's no synchronized sampling, because the receiver may sample the signal when it's in the forbidden zone between 0 and 1, which if you're unlucky causes a cascade of gates floating at an indeterminate state rather than latching to a binary level.",
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