📅 Original date posted:2017-04-09
📝 Original message:On 04/09/2017 05:20 PM, Erik Aronesty via bitcoin-dev wrote:
> Have you read the cuckoo cycle paper? Finding cycles in massive graphs
> is just about the worst thing to use an ASIC for.
It's actually the best thing to use an ASIC tightly coupled with DRAM
for - for example, HBM and HBM2 which reduce latency and increase
throughput by placing the DRAM on an interposer with the ASIC die, or
even putting the logic on the DRAM die itself.
It would need at least proof that existing chips using HBM are ideal for
Cuckoo Cycle (unlikely) and that no DRAM manufacturer could ever be
coaxed into making an ASIC (even harder to guarantee).
I think any long term PoW change is irrelevant to the review or adoption
of the covert ASICBOOST BIPs, given the many unresolved problems of such
a change.
Thomas Daede [ARCHIVE] /
npub1vj…3qpuy
2023-06-07 17:59:52
in reply to nevent1q…zy50
Author Public Key
npub1vjlv5yhutdz826l4nqyrc9v72wjzp0d3j48y7d429fkh9xquew4sx3qpuyPublished at
2023-06-07 17:59:52Event JSON
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"content": "📅 Original date posted:2017-04-09\n📝 Original message:On 04/09/2017 05:20 PM, Erik Aronesty via bitcoin-dev wrote:\n\u003e Have you read the cuckoo cycle paper? Finding cycles in massive graphs\n\u003e is just about the worst thing to use an ASIC for.\n\nIt's actually the best thing to use an ASIC tightly coupled with DRAM\nfor - for example, HBM and HBM2 which reduce latency and increase\nthroughput by placing the DRAM on an interposer with the ASIC die, or\neven putting the logic on the DRAM die itself.\n\nIt would need at least proof that existing chips using HBM are ideal for\nCuckoo Cycle (unlikely) and that no DRAM manufacturer could ever be\ncoaxed into making an ASIC (even harder to guarantee).\n\nI think any long term PoW change is irrelevant to the review or adoption\nof the covert ASICBOOST BIPs, given the many unresolved problems of such\na change.",
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