mos_8502 :verified: on Nostr: The fact that latching based on PHI2 and R/W rather than /RD and /WR from the glue ...

The fact that latching based on PHI2 and R/W rather than /RD and /WR from the glue logic (thus buying a few more nanoseconds) seems to have "fixed" it at 8MHz (in that the glitching goes away) would *seem* to indicate that clock domains *is* the issue -- on a cycle where things are *just* far enough into the danger zone, and everything goes *just* wrong enough, it ends up latching the data bus when it's already decaying or before it's settled.