mos_8502 :verified: 🇨🇦 on Nostr: Okay. So in the default configuration, the VERA uses a 25MHz SYSCLK input as its ...

Okay. So in the default configuration, the VERA uses a 25MHz SYSCLK input as its internal clock. It interfaces with the bus through the usual /CE, /RD, /WR address and data bus latching you would expect. This generally works with 6502 systems, especially under about 8MHz. However, because the CPU bus and the VERA's internals have separate clocks, one 25MHz and the other 8MHz, from different oscillators, they are out of phase; thus, so the theory goes, when the clocks are too far apart, a write or read can get the wrong data.

The solution for this we have now is to alter how VERA talks to the bus; by replacing /RD and /WR with R/W and the CPU's PHI2 output, and duplicating the conditions for read and write signals from the glue logic inside the FPGA, we buy enough time to make that 8MHz more reliable.

However, I have the idea to solve the phase problem by making the two clocks synchronous -- feed the 25MHz SYSCLK into VERA as normal, and divide it internally by 3 to get an 8.333MHz FCLK output fed to the CPU as the main clock source. Thus, every CPU cycle is in phase with a VERA cycle -- at least in theory. The FPGA would then use the internal FCLK generated from the SYSCLK and the R/W input to latch the address and data bus with /CE; the CPU sees no change at all, beyond a slightly faster clock.

If that turns out to work, then the next phase of the experiment is to divide SYSCLK by two instead of three, for a 12.5MHz FCLK. The CPU is known to be able to handle that, but it is unclear whether or not the VERA bus interface can take it. I am dubious about it, but I feel it's worth at least the attempt.