Event JSON
{
"id": "71ff970333117391e55ee00d77b04e2cf988f714a0f693940a06a1895a88a2e2",
"pubkey": "6175da632a8c9187a4368f0c8ad67b8a6e884f16d456954ba53b1d60696c4079",
"created_at": 1692564730,
"kind": 1,
"tags": [
[
"p",
"fb963a709816d4f9fdec6d5375d788a29cd346a6eac195cdb3ae104d01ebc59f",
"wss://relay.mostr.pub"
],
[
"p",
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],
[
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"wss://relay.mostr.pub"
],
[
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],
[
"e",
"258ab3228da899dee533f1f4b0cb28d0acaf4769cc3c58e17dcafe945e902640",
"wss://relay.mostr.pub",
"reply"
],
[
"proxy",
"https://clubcyberia.co/objects/1095f516-883b-467c-9671-8e226026146e",
"activitypub"
]
],
"content": "nostr:npub1lwtr5uyczm20nl0vd4fht4ug52wdx34xatqetndn4cgy6q0tck0s6wq3ry nostr:npub106dam65ww9ztdqj26xvh08dyuc7lj7nmkrtrujwsmyq2n6g3r33saq3m89 nostr:npub176cjqxztl6h6h3qldvwln38rwlw50aprq2fedadz45w9evvee2fqhem880 nostr:npub1psx7zml4neu6v03fe6pqcdp4lvcf444mfswy4rlfz28s8jwtzjtqrxgvsy For simple logic chips you could implement them directly as a logic circuit diagram, but for most modern logic chips, they are implemented in a hardware description language like VHDL or verilog. They most likely use a mixture of HDL and CAD tools to manage the overall design and then synthesize it into an actual chip layout.",
"sig": "ab5d41e97c5c8590f8fe2257042c089bddf1b00f77f3c5514655567a51f85d6ecc91ce5341bcc69e58d162266c0e770a792a01f79b6efc698ffab9a6268da3b6"
}