Dave Anderson on Nostr: What I can say prior to that... If you make the vera generate FCLK from its own ...

What I can say prior to that... If you make the vera generate FCLK from its own reference, I could see that helping by keeping the two domains phase-locked somewhat (modulo propagation delays across the board etc.). Assuming the glitch is indeed caused by clock phases sliding around due to not being multiples of each other, locking them together would do the thing. Fingers crossed!