In the currently extant prototypes, the CPU has two oscillators (32.768KHz and 8MHz) and the FPGA has its own 25MHz oscillator.
What I *want* to do is instead have the FPGA generate a CPU clock from its own internal clock, forcing the two to be in lockstep. I have a prototype PCB on the way which implements this, but I will need to build it and figure out how to make the VERA core do the thing (output SYSCLK/2 or SYSCLK/3 from PHI2 rather than take the clock output from the CPU as input).
mos_8502 :verified: 🇨🇦 /
npub1qn…5hzwk
2024-08-17 20:38:10
in reply to nevent1q…ktel
Author Public Key
npub1qnufz4pycufk27kkeev5g0fgm0w0tqexsly674s2uwy0tynk5ymsk5hzwkPublished at
2024-08-17 20:38:10Event JSON
{
"id": "a6e18a55d2e6ef02c2a14a27039b9282484e43e1b562e189c6c2ef77c4981052",
"pubkey": "04f8915424c713657ad6ce59443d28dbdcf5832687c9af560ae388f59276a137",
"created_at": 1723927090,
"kind": 1,
"tags": [
[
"e",
"f68f3c3e481d36ea2a2869cf25dfc341c3243d3f1f4f54189ab0a736923211d7",
"",
"reply",
"dad113f50e47d6bffb79f9a69006ffd969c26e636e5aed2ae597b0407093175f"
],
[
"p",
"04f8915424c713657ad6ce59443d28dbdcf5832687c9af560ae388f59276a137"
],
[
"p",
"dad113f50e47d6bffb79f9a69006ffd969c26e636e5aed2ae597b0407093175f"
],
[
"e",
"77ba25bd8c3ce6cb748702bc3130c078db0af0c24a5a562695ced00e95bd3073",
"",
"root",
"dad113f50e47d6bffb79f9a69006ffd969c26e636e5aed2ae597b0407093175f"
],
[
"proxy",
"https://studio8502.ca/@mos_8502/112979285784111300",
"web"
],
[
"proxy",
"https://studio8502.ca/users/mos_8502/statuses/112979285784111300",
"activitypub"
],
[
"L",
"pink.momostr"
],
[
"l",
"pink.momostr.activitypub:https://studio8502.ca/users/mos_8502/statuses/112979285784111300",
"pink.momostr"
],
[
"-"
]
],
"content": "In the currently extant prototypes, the CPU has two oscillators (32.768KHz and 8MHz) and the FPGA has its own 25MHz oscillator.\n\nWhat I *want* to do is instead have the FPGA generate a CPU clock from its own internal clock, forcing the two to be in lockstep. I have a prototype PCB on the way which implements this, but I will need to build it and figure out how to make the VERA core do the thing (output SYSCLK/2 or SYSCLK/3 from PHI2 rather than take the clock output from the CPU as input).",
"sig": "cb65a1122979b938453df922c9d539e00002f59273f535d27b061b52f7ae44748d56ae6c83a764c7732da209b9ca73760deef39ed4383c82d7997729ba72399b"
}